In semiconductor circuits, interconnect layers or multilevel metallization is necessary for the proper operation of the various devices fabricated. Interconnect signal lines make contact with lower conductive layers in the integrated circuit through vias in an insulating layer. For best operation of the devices, the lower conductive layer cannot be damaged during formation of the contact vias.
Various interlevel insulating layers are deposited on the integrated circuit during formation of the devices. These layers separate the conductive layers from each other. One method to form contact vias through these insulating layers utilizes a photoresist layer to define the via locations. An anisotropic etch is then performed to open the vias. Due to the increased topography of submicron devices, the thicknesses of the interlevel insulating layers are significantly different in various regions of the die. The differences in thicknesses requires prolonged etching of the insulating layers to insure good electrical contact in all of the vias. During the prolonged anisotropic etch, however, the etch chemistry causes a chemical reaction to take place between the photoresist, the interlevel insulating layers and the lower conductive layer. Typically, during the etch process, polymers are created which adhere to the sidewalls of the via.
As known in the prior art, the polymers are removed or dissolved through the use of a solvent, acid or plasma etch. Due to the submicron dimensions of the vias and the restriction on use of caustic chemicals, the removal of these polymers poses a formidable task. Retaining any of the polymer build up causes difficulties in achieving high standards of reliability of the devices. Removal of all of the polymeric material, however, may result in a substantial amount of the underlying conductive layer to be removed. Additionally, the acid or plasma etch can remove some of the insulating layer, which enlarges the size of the via.
Therefore, it would be desirable to provide a technique for forming contact vias in integrated circuits which prevents the formation of such polymeric films.